DMOS transistors, particularly of the vertical type, are important in power device applications capable of handling high voltages. For such devices, the figure of merit is the current handling capability per unit area or the ON resistance per unit area. For a given voltage rating, the ON resistance per unit area may be reduced by reducing the cell area of the DMOS device.
In the field of power transistors, the combined width of the polycrystalline silicon (polysilicon) and the contact region, which forms the gate and source electrodes, respectively, is defined as the cell pitch of the device. For a DMOS power transistor, a known technique to reduce the width of the polysilicon region is by decreasing the P-well junction depth. However, minimum junction depth is dictated by the breakdown voltage required. Therefore, further cell size reduction must come from reducing the size of the contact area of the device.
Therefore, a need has arisen for reducing the contact area of a vertical DMOS device to further minimize the overall cell pitch of the device, which in turn enhances its current handling per unit area capabilities. The present invention provides a DMOS transistor and a new semiconductor manufacturing process which enable a reduction of the contact area of the DMOS device so that its ON resistance per unit area is decreased.